(來源:下載頻道)
jida_song 2012-5-17 09:28
jida_song 2012-5-15 11:24
jida_song 2011-11-11 16:25
jida_song 2011-11-8 08:52
簡易通用型PCI接口的VHDL-CPLD設計 (來源:下載頻道)
jida_song 2011-1-28 17:07
基于CPLD的單片機PCI接口設計 (來源:下載頻道)
jida_song 2011-1-28 15:59
This directory has the rtl (Verilog) associated with the MAX II PCI reference design. top_pci32.v is the top level of the design. The core directory contains the wizard .generated files for the 32-bit/33 MHz PCI Target.The local irectory has all the files for local reference desi... (來源:下載頻道)
網絡資源 2007-12-21 13:14